Designing AI inference chips? From floorplanning to power delivery, here are the physical design considerations that matter. AI inference workloads are becoming more compute-intensive, with higher demands on throughput, memory access, and power efficiency. AI inference chips are placing new demands on physical design. Compute is becoming denser, SRAM is moving closer to compute, data paths are becoming wider, and local power density is increasing. As a result, floorplanning, power delivery, clocking, routing, and thermal management all must work together. The physical design decisions made early in the flow can directly affect performance, power, and scalability.